1. Technical Field
The present invention relates in general to data processing systems, and in particular to a method and system for data transfer within a data processing system. Still more particularly, the present invention relates to a method and system for enhanced data transfer in a data processing system having separate address spaces for input/output devices and memory.
2. Description of the Related Art
Designers of modern state-of-the-art data processing systems are continually attempting to enhance the performance aspects of such systems. One technique for enhancing data processing system efficiency is the utilization of separate memory and input/output (I/O) addresses. Furthermore, it is common to use separate buses for memory and I/O transactions.
Separate buses, however, are expensive to implement due to the need for increased pin outs for the separate buses. Therefore, it is desirable to perform both memory and I/O transfers on a single bus. Using a single bus for both memory and I/O transfers, however, increases the complexity of the system because memory and I/O transactions are very different. I/O transfers must provide synchronous error detection and strict ordering. Strict ordering means the transfers must run on the address bus in the order of the instruction stream. One consequence of strict ordering is that I/O transfers may reduce the performance potential of a system because latency for I/O transfers typically is much larger than latency for memory transfers. Latency for I/O transfers are larger because accessing I/O devices usually takes longer. Latency refers to the time interval between the instant at which an instruction control unit initiates a call for data and the instant at which the actual transfer of the data starts.
Another technique utilized for enhancing data processing system efficiency is memory mapping. Memory mapping requires that I/O addresses be decoded before the I/O transfer can occur. Typically, this factor limits I/O addresses to 32 bits. Another disadvantage to memory mapping is that it requires a synchronization instruction be given for each I/O transfer. Finally, memory mapping typically does not provide for error reporting when there is a problem with an I/O device during a transfer.
Therefore, a need exists for a method and system of enhanced data transfer in a data processing system which utilizes a single bus interface for both memory and I/O transfers. It is also desirable that such a method and system maintain strict ordered accesses and error detection.